Design and Practice of Efficient Acceleration System for YOLOv8 Object Detection Algorithm Based on FPGA

DOI: https://doi.org/10.62517/jike.202604225

Author(s)

Qicheng Wen

Affiliation(s)

Electronic Information Science and Technology School of Physics Chongqing University, Chongqing, China

Abstract

This paper addresses the performance bottleneck of the YOLOv8 object detection algorithm in real-time applications by proposing an efficient FPGA-based acceleration system design. First, the system reviews the current state of object detection algorithms and FPGA technology, analyzing the shortcomings of existing FPGA acceleration solutions. Second, at the system design level, it focuses on optimization strategies for the YOLOv8 algorithm, including network structure simplification and computational flow reconstruction, and completes the selection and configuration design of the FPGA hardware platform. In the implementation phase, the paper elaborates on the algorithm’s migration process to FPGA and the hardware circuit implementation, including PCB design. Experimental results demonstrate that the designed acceleration system significantly improves processing speed while maintaining detection accuracy, validating the effectiveness of FPGA hardware acceleration. Finally, the paper discusses key factors influencing system performance optimization and identifies future improvement directions, such as algorithm-hardware co-design and dynamic reconfiguration. This study provides an efficient hardware acceleration solution for real-time object detection applications, offering significant theoretical value and practical implications.

Keywords

FPGA; Object Detection; YOLOv8; Hardware Acceleration; Real-Time Performance.

References

[1] XIAO Yang. Research on FPGA Reverse Consistency Verification Technology [J]. China Master's Theses Full-text Database, 2025. [2] TIAN Jiayu. Research on Single Event Effect and Fault Propagation of SRAM-based FPGA Devices [J]. China Master's Theses Full-text Database, 2025. [3] LIANG Shiyan. Research on Routing Optimization Algorithm for TDM-driven Multi-FPGA Systems [J]. China Master's Theses Full-text Database, 2025. [4] LING Ming, et al. Vina-FPGA2: A Molecular Docking Tool Based on Inter-module Pipelined High-level Parallel Hardware Acceleration [J]. Frontiers of Information Technology & Electronic Engineering, 2025. [5] WANG Haoxuan. Research on Channel Pruning and FPGA Acceleration Methods for Convolutional Neural Networks [J]. China Doctoral Dissertations Full-text Database, 2025. [6] LIU Yuhang. Optimized Design of Canny Algorithm Based on FPGA [J]. China Master's Theses Full-text Database, 2025. [7] ZHANG Kuan. Hardware Circuit Design of TTE End-system Interface Carrier Board Based on FPGA [J]. China Master's Theses Full-text Database, 2025. [8] LIU Junyue. Research on Time Synchronization Technology of Low-orbit Satellite Broadband OFDM Signals Based on FPGA [J]. China Master's Theses Full-text Database, 2025. [9] DENG Yuanyuan. Research on Convolutional Neural Network Accelerator Based on FPGA [J]. China Master's Theses Full-text Database, 2025. [10] YANG Wei. Research on Graph Convolutional Neural Network Algorithm and Its Implementation Based on FPGA [J]. China Master's Theses Full-text Database, 2025. [11] LUO Chuang. Design and Implementation of Online Remote Experimental Platform Based on FPGA [J]. China Master's Theses Full-text Database, 2025. [12] LIANG Jiaxin. Research on Region of Interest Compression Method of Star Map Based on FPGA [J]. China Master's Theses Full-text Database, 2025. [13] DONG LIU Y Y. CXL-SpecKV: A Disaggregated FPGA Speculative KV-Cache for Datacenter LLM Serving [J]. 2025-12-11. [14] SHULIN ZENG G D Jun Liu. FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs [J]. 2024-01-08. [15] BROWN N. Accelerating advection for atmospheric modelling on Xilinx and Intel FPGAs [J]. 2021-07- [16] NICK BROWN O T B Mark Klaisoongnoen. Optimisation of an FPGA Credit Default Swap engine by embracing dataflow techniques [J]. 2021-07-28. [17] PINGAKSHYA GOSWAMI D B. Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs [J]. 2020-11-23. [18] JONAS DANN H F Daniel Ritter. Non-Relational Databases on FPGAs: Survey, Design Decisions, Challenges [J]. 2020-07-15. [19] MACIEJ BESTA T B-N Marc Fischer. Substream-Centric Maximum Matchings on FPGA [J]. TRETS, 2020. [20] HANQING ZENG V P. GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms [J]. 2019-12-31. [21] SUMANTA CHAUDHURI P H Sylvain Guilley. A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback [J]. 2011-03-07.