Optimization of Signal Source and Clock Source Combination for ADC Chip Test Based on V93000 Platform

DOI: https://doi.org/10.62517/jes.202602229

Author(s)

Xinyang Ding

Affiliation(s)

Department of Integrated Circuits, North China University of Technology, Beijing, China

Abstract

In the development and verification of high-speed and high-precision Analog-to-Digital Converters (ADCs), the configuration of the test platform is critical for obtaining accurate and repeatable dynamic performance data. During the testing of a high-performance ADC, significant performance fluctuations were observed under different combinations of clock sources and signal sources, which affected the accuracy of performance evaluation and the stability of mass production testing. To address this issue, this paper optimizes the mixed-signal test platform through clock source selection and signal source matching. Based on the V93000 SmarTest 8 platform, this study investigates a high-speed 4- channel ADC with a resolution of 16 bits and a sampling rate of 125 Msps. Two clock schemes, namely Oscillator (OSC) and PS1600, as well as two signal sources, namely WaveScale MX (WSMX) and Signal Generator SMA100B, are comparatively studied. Key performance indicators, including Signal-to-Noise Ratio (SNR), Signal-to-Noise Ratio relative to Full Scale (SNR-dBFS), and Total Harmonic Distortion (THD), are evaluated under input frequencies of 10 MHz and 300 MHz. The experimental results demonstrate that OSC exhibits better phase noise and jitter performance than PS1600, while SMA100B provides higher spectral purity than WSMX. The optimal combination of OSC and SMA100B effectively reduces spectrum leakage and jitter interference, thereby achieving more stable ADC dynamic performance testing. This paper proposes an optimized test platform configuration scheme, which provides a reliable reference for ADC verification, load board design, and mass production testing.

Keywords

High-speed ADC; SMA100B; WSMX; PS1600; V93000; SmarTest 8.

References

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