A Literature Review on Low-Power Optimization of CMOS Temperature Sensors

DOI: https://doi.org/10.62517/jes.202602235

Author(s)

Yuxuan Ling

Affiliation(s)

College of Physics Science and Technology, Yangzhou University, Yangzhou, China

Abstract

With the rapid development of the Internet of Things and mobile devices, the demand for continuous accurate and low power consumption temperature monitoring has increased significantly. Therefore, CMOS temperature sensors have attracted wide attention because of their compatibility with IC technology, low cost and high integration. How to achieve low energy consumption under the premise of ensuring measurement performance has become a core design challenge. The strict power consumption requirements of application scenarios such as limited power supply, long-term standby and intermittent sampling have promoted the transformation of sensors to low power optimization. It has become a core issue to study how to achieve a compromise and balance between power consumption, accuracy, response speed and area. CMOS temperature sensors have been widely used in portable electronic devices, Internet of things nodes, wearable terminals and on-chip thermal monitoring due to their compatibility with standard integrated circuit processes, low cost, small area, and easy integration with system-on-chip. In recent years, with the continuous development of edge intelligence and distributed sensing systems, low-power optimization has gradually become one of the core issues in the design of temperature sensing circuits. Focusing on the low power optimization problem of CMOS temperature sensor, this paper systematically expounds the collaborative optimization strategy of key modules such as temperature sensing front-end, signal processing circuit, analog-to-digital converter (ADC), digital filter and system architecture. In the thermal front-end, the exponential characteristics of sub-threshold MOSFETs are used to achieve nanoamperes static power consumption, and the dynamic biasing technology is combined to reduce the average power consumption. At the same time, how to maintain good linearity under very low bias current is analyzed. In the signal conditioning and ADC link, time domain technologies such as dynamic comparator and voltage to time conversion are used to replace the traditional high power consumption structure, and SAR or TDC architectures are optimized for different resolution requirements to realize the digitization of temperature signals with lower power consumption. At the system level, this paper summarizes the top-level energy efficiency design schemes, such as periodic wake-up mechanism, fast start circuit, and one-bus digital interface, which reduce the average power consumption in standby and working states. Through literature research and comparative analysis, this paper sorts out the research results at home and abroad in the past two decades, constructs a technology evolution framework for CMOS temperature sensor low-power optimization, and quantitatively compares the power reduction effects of various methods. Research shows that multi-module collaborative optimization can break through the limitations of single circuit improvement, and provide energy-efficient and highly-integrated low-power optimization solutions for temperature sensors in application scenarios such as Internet of things, wearable devices and battery management systems.

Keywords

CMOS Temperature Sensor; Low Power Optimization; Subthreshold Technique; Dynamic Bias; System Architecture

References

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